Title :
On the design of path delay fault testable combinational circuits
Author :
Pramanick, Ankan K. ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., IA, USA
Abstract :
A theoretical framework for investigating the design for the path-delay-fault testability problem is provided. Necessary and sufficient conditions for the existence of general robust tests in a multioutput, multilevel circuit are given. The conditions for the existence of a more restricted class of robust tests are derived from those for general robust tests. A design procedure is given for the synthesis of multioutput, multilevel combinational logic circuits in which all path delay faults are robustly detectable. A powerful factorization method, that of extended factorization, was exploited for this purpose.<>
Keywords :
logic circuits; logic testing; design; logic circuits; necessary and sufficient conditions; path delay fault testable combinational circuits; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Design for testability; Electrical fault detection; Logic testing; Propagation delay; Robustness; Sufficient conditions;
Conference_Titel :
Fault-Tolerant Computing, 1990. FTCS-20. Digest of Papers., 20th International Symposium
Conference_Location :
Newcastle Upon Tyne, UK
Print_ISBN :
0-8186-2051-X
DOI :
10.1109/FTCS.1990.89391
