Prediction model for estimating leakage power consumption of routing resources in FPGAs

Leakage power in nano-scale technologies is an important source of power consumption. Moreover, FP-GAs with low utilization rates consume large leakage power in their routing and logical resources. As FPGA routing architecture incorporates large number of transistors, leakage power of routing resources contributes the majority of total leakage power consumption. In this paper, a pre-routing prediction model is proposed for estimating leakage power consumption of routing resources. Several parameters are used in the prediction model by analyzing their impacts on the leakage power consumption of routing resources. In addition to these parameters, the behavior of FPGA routers on different nets is estimated and considered in the prediction model. The proposed prediction model can be used in pre-routing power optimization techniques such as power-aware placement algorithms. Simulation results for 10 MCNC benchmarks show that the mean error rate of the proposed prediction model is about 28.8% for the FPGAs with 60% utilization rate.