Title :
A novel and fast method for characterizing noise based PCMOS circuits
Author :
Singh, Anshul ; Mandavalli, Satyam ; Mooney, Vincent J., III ; Ling, Keck-voon
Abstract :
Quick and accurate error-rate prediction of Probabilistic CMOS (PCMOS) circuits is crucial for their systematic design and performance evaluation. While still in early stage of research, PCMOS has shown potential to drastically reduce energy consumption at a cost of increased errors. Recently, a methodology has been proposed which could predict the error-rates of cascade structures of blocks in PCMOS. It requires error-rates of unique blocks to predict the error-rates of a multi-block cascade structure. The “Three stage model,” which accounts for different noise filtering for different paths in a circuit, has been proposed to characterize unique blocks. While the results obtained from the three stage model produced accurate error-rates for a multi-block cascade structure, the procedure for its characterization is computationally expensive. In this paper, we propose a new method for characterizing the three stage model that not only provides accurate results but is also computationally cheap.
Keywords :
CMOS integrated circuits; filtering theory; integrated circuit design; integrated circuit modelling; integrated circuit noise; PCMOS circuits; energy consumption; error-rate prediction; multiblock cascade structure; noise characterization; noise filtering; probabilistic CMOS circuit; systematic design; three stage model; Computational modeling; Gaussian noise; Integrated circuit modeling; Logic gates; Predictive models; Probabilistic logic; PCMOS circuits; characterization; dynamic noise analysis;
Conference_Titel :
Quality Electronic Design (ASQED), 2011 3rd Asia Symposium on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4577-0145-0
DOI :
10.1109/ASQED.2011.6111738