Reliability analysis of digital circuits considering intrinsic noise

The scaling of digital CMOS circuits into the nanometer region causes an increase in intrinsic device noise. Existing methods to analyze the impact of noise on circuit performance use analytical estimations based on simplified cell models. In this paper we propose a characterization method for the impact of intrinsic noise based on SPICE simulation. The method considers all major noise sources in integrated circuits and is able to determine the effect of intrinsic noise on circuit reliability. Contrary to existing methods, it is general enough to analyze different logic implementation styles and device technologies. Additionally it is shown that previous methods overestimate the influence of intrinsic noise up to a factor of 4.