Inter-frame Laplacian pyramid coding for video compression

The question of algorithm selection is addressed and the arguments which lead to the development of a novel sub-band coding approach are presented. The authors describe the implementation of the algorithm on a realtime demonstrator, based on an array of transputers. They then describe the dedicated image/video processing board, based on the Inmos A110 2D filter chip, which has been developed at BAe to perform much of the intensive processing and which is being integrated with the realtime demonstrator to replace many of the transputers in the array and to allow larger image sizes to be processed with greater flexibility. Finally the authors address the issue of the development of more dedicated hardware, and present some examples of current applications of the method