Title :
MHERTZ: a new optimization algorithm for floorplanning and global routing
Author :
Brasen, Daniel R. ; Bushnell, Michael L.
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
Abstract :
Timing-driven placement is essential for full-custom VLSI, gallium arsenide, and ECL circuits to meet wire timing constraints. A new macro/custom cell floorplanner and global router, called MHERTZ, is described. It meets wire timing constraints by using force-directed cost functions in multistart and simulated annealing (SA) optimization algorithms. MHERTZ also prevents wire coupling, meets specified chip aspect ratios, and produces smaller floorplans than TIMBERWOLFMC
Keywords :
VLSI; circuit layout CAD; emitter-coupled logic; optimisation; ECL circuits; chip aspect ratios; floorplanning; force-directed cost functions; full-custom VLSI; global routing; optimization algorithm; simulated annealing; wire timing constraints; Circuit simulation; Cost function; Force measurement; Integrated circuit interconnections; Pins; Routing; Simulated annealing; Timing; Very large scale integration; Wire;
Conference_Titel :
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-89791-363-9
DOI :
10.1109/DAC.1990.114838
