• DocumentCode
    276232
  • Title

    HART, a heterogeneous architecture for real-time image processing

  • Author

    Goodenough, J. ; Seed, N.L.

  • Author_Institution
    Sheffield Univ., UK
  • fYear
    1992
  • fDate
    7-9 Apr 1992
  • Firstpage
    590
  • Lastpage
    593
  • Abstract
    Today, real-time image processing hardware primarily takes the form of a high speed front end accelerator, targetted toward iconic and intermediate level algorithmic tasks. Examples of contemporary commercial systems are: Datacube, Maxtor and, Data Translation (for PC); Microsystem Mainboard, and Analogic (for VME). These are supported by a range of software environments, such as Visilog or Semper, which permit pre-defined library routines to be executed in a user friendly environment. In some cases, the hardware supports complex operations ranging from morphological operators to stereo vision algorithms. Whilst addressing a required market niche and pushing image processing into real applications, these products are inherently limited by the host machine´s processing power and the interconnection topology adopted within the hardware itself. The authors describe a new architecture which is designed to address these problems and evolve to match the requirements of dynamic scene analysis and understanding
  • Keywords
    computerised picture processing; real-time systems; HART; dynamic scene analysis; heterogeneous architecture; real-time image processing;
  • fLanguage
    English
  • Publisher
    iet
  • Conference_Titel
    Image Processing and its Applications, 1992., International Conference on
  • Conference_Location
    Maastricht
  • Print_ISBN
    0-85296-543-5
  • Type

    conf

  • Filename
    146867