Title :
Timed trace theoretic verification using partial order reduction
Author :
Yoneda, Tomohiro ; Ryu, Hiroshi
Author_Institution :
Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan
Abstract :
In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently
Keywords :
Petri nets; asynchronous circuits; circuit analysis computing; formal verification; set theory; timing; STARI circuits; Stubborn set method; partial order reduction algorithm; time Petri nets; timed asynchronous circuits; timed specification; timed trace theoretic verification; timing analysis; Clocks; Petri nets;
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings., Fifth International Symposium on
Conference_Location :
Barcelona
Print_ISBN :
0-7695-0031-5
DOI :
10.1109/ASYNC.1999.761527
