Title :
A900MHz-2GHz low-swing low-power 0.18/spl mu/m CMOS PLL
Author :
Nouri, Neda ; Mirabbasi, Shahriar
Author_Institution :
Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC
Abstract :
A fully integrated differential charge-pump phase-locked loop (PLL) is described. The PLL is designed, simulated, and laid out in a 0.18 mum CMOS technology. The PLL lock range is form 900 MHz to 2 GHz. All of the PLL internal signals are differential and low swing (1 V peak-to-peak differential voltage swing). To further reduce the power consumption of the PLL, the charge pump current of 15 muA is used. The PLL operates from a 1.8 V supply while consuming less than 10.5 mW. The complete PLL including its on-chip loop filter occupies 100times190mum2
Keywords :
CMOS integrated circuits; UHF integrated circuits; low-power electronics; phase locked loops; 0.18 micron; 1.8 V; 900 MHz to 2 GHz; CMOS PLL; integrated differential charge-pump phase-locked loop; on-chip loop filter; peak-to-peak differential voltage swing; power consumption reduction; CMOS technology; Charge pumps; Circuit noise; Clocks; Filters; Latches; Phase detection; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Electrical and Computer Engineering, 2005. Canadian Conference on
Conference_Location :
Saskatoon, Sask.
Print_ISBN :
0-7803-8885-2
DOI :
10.1109/CCECE.2005.1557278
