Title :
Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits
Author :
Oakland, Steven F.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
This paper addresses four issues associated with using IEEE Standard 1149.1 on system-on-a-chip integrated circuits (SOC ICs). First, a new, simplified method for accessing debug registers in processor cores embedded within ICs is presented. Second, structural information required by hardware/software processor development tools is presented. Third, issues associated with boundary-scan description language (BSDL) are discussed. Finally, high-speed boundary-scan cells that avoid a multiplexer delay are presented
Keywords :
IEEE standards; boundary scan testing; integrated circuit testing; microprocessor chips; IEEE 1149.1 standard; boundary-scan description language; debug register; embedded processor core; high-speed boundary-scan cell; structural testing; system-on-a-chip integrated circuit; Clocks; Delay; Logic testing; Microelectronics; Multiplexing; Object recognition; Pins; Shift registers; System-on-a-chip; USA Councils;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894257
