Title :
An inductor with taper stacked metals on silicon chip
Author_Institution :
VIA Technol., Inc., Hsin-Tien
Abstract :
A taper stacked metal structure has been investigated on the silicon substrate. Compared with the conventional stacked metal structure, it can have the comparable conductor loss and lower unwanted couplings. Parasitic capacitances and induced eddy currents on silicon substrate can then be efficiently reduced. The inductor with the proposed structure has been proved to have an improved Q with a moderate roll-off and a smaller influence on the inductance. Electromagnetic simulation, equivalent circuit modeling, and measurement have been taken for the validation.
Keywords :
CMOS integrated circuits; Q-factor; eddy currents; elemental semiconductors; equivalent circuits; inductance; inductors; integrated circuit design; silicon; eddy currents; electromagnetic simulation; equivalent circuit modeling; inductor; parasitic capacitances; silicon chip; silicon substrate; taper stacked metals; Circuit simulation; Conductors; Coupling circuits; Eddy currents; Electromagnetic modeling; Equivalent circuits; Inductance; Inductors; Parasitic capacitance; Silicon; CMOS integrated circuits; Q factor; inductors; semiconductor devices;
Conference_Titel :
Microwave Conference, 2006. APMC 2006. Asia-Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-4-902339-08-6
Electronic_ISBN :
978-4-902339-11-6
DOI :
10.1109/APMC.2006.4429700
