DocumentCode :
2763672
Title :
A comparison of classical scheduling approaches in power-constrained block-test scheduling
Author :
Muresan, Vlad ; Xiaojun Wang ; Muresan, Vlad ; Vladutiu, Mircea
Author_Institution :
Dublin City Univ., Ireland
fYear :
2000
fDate :
2000
Firstpage :
882
Lastpage :
891
Abstract :
Classical scheduling approaches are applied here to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. List scheduling-like approaches are proposed first as greedy algorithms to tackle the fore mentioned problem. Then, distribution-graph based approaches are described in order to achieve balanced test concurrency and test power dissipation. An extended tree growing technique is also used in combination with these classical approaches in order to improve the test concurrency having assigned power dissipation limits. A comparison between the results of the test scheduling experiments highlights the advantages and disadvantages of applying different classical scheduling algorithms to the power-constrained test scheduling problem
Keywords :
VLSI; automatic testing; integrated circuit testing; logic design; logic testing; power supply circuits; trees (mathematics); BIST; VLSI; balanced test concurrency; distribution-graph; extended tree growing technique; mean square error; power-constrained block-test scheduling; power-constrained test scheduling; pseudocode; scheduling algorithms; test power dissipation; trees; unequal-length block-test scheduling; Circuit testing; Concurrent computing; Greedy algorithms; Partitioning algorithms; Polynomials; Power dissipation; Scheduling algorithm; System testing; Tree graphs; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
ISSN :
1089-3539
Print_ISBN :
0-7803-6546-1
Type :
conf
DOI :
10.1109/TEST.2000.894299
Filename :
894299
Link To Document :
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