Title :
Hot carrier effects in nMOSFETs in 0.1 μm CMOS technology
Author :
Li, E. ; Rosenbaum, E. ; Tao, J. ; Yeap, G.C.-F. ; Lin, M.R. ; Fang, P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
Recent studies show that, for a given technology, as the effective channel length is scaled down towards 0.1 μm, the worst case hot carrier stress condition for nMOSFETs switches from Ib, peak (peak substrate current bias condition) to Vg=Vd. In this paper, we demonstrate that the worst case stress condition is determined by the ratio of Ib| Ib, peak to Ib|Vg=Vd. Post-metallization anneal in deuterium similarly improves hot carrier lifetime under bias at Ib, peak and Vg=Vd
Keywords :
CMOS integrated circuits; MOSFET; annealing; electric current; hot carriers; semiconductor device metallisation; semiconductor device reliability; semiconductor device testing; 0.1 micron; CMOS technology; D2; deuterium anneal; effective channel length scaling; hot carrier effects; hot carrier lifetime; hot carrier stress condition; nMOSFETs; peak substrate current bias condition; post-metallization anneal; worst case stress condition; Annealing; CMOS technology; Degradation; Electron traps; Hot carrier effects; Hot carriers; MOSFETs; Space technology; Stress; Voltage;
Conference_Titel :
Reliability Physics Symposium Proceedings, 1999. 37th Annual. 1999 IEEE International
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5220-3
DOI :
10.1109/RELPHY.1999.761622
