Title :
Architecture of a general-purpose neural signal processor
Author :
Ramacher, U. ; Beichter, J. ; Brüls, N.
Author_Institution :
Siemens AG, Munich, West Germany
Abstract :
A versatile neurocomputer architecture must absorb in silicon the elementary compute-bound algorithmic strings shared by all known neural paradigms. The digital neural signal processor MA16 was designed to execute this set of compute-bound algorithmic operations. Its architecture and the technology chosen allow for a computing power of 800 million connections per second (1 C=16 b) at a worst-case clock rate of 40 MHz. At the board level the system performance can be augmented by means of one- or two-dimensional arrays of these chips. The neural signal processor architecture was designed as an integral part of a neurocomputer system architecture which comprises a systolic array of MA16s
Keywords :
digital signal processing chips; neural nets; 50 MHz; MA16; compute-bound algorithmic strings; digital neural signal processor; neurocomputer architecture; one dimensional arrays; silicon; systolic array; two-dimensional arrays; worst-case clock rate; Algorithm design and analysis; Clocks; Computer architecture; Process design; Signal design; Signal processing; Signal processing algorithms; Silicon; System performance; Systolic arrays;
Conference_Titel :
Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-0164-1
DOI :
10.1109/IJCNN.1991.155218