A parallel analog CCD/CMOS neural network IC

Author

Neugebauer, Charles F. ; Yariv, Amnon

Author_Institution

Dept. of Appl. Phys., California Inst. of Technol., Pasadena, CA, USA

Volume

i

fYear

1991

fDate

8-14 Jul 1991

Firstpage

447

Abstract

A mixed analog/digital neural network chip is presented that uses standard 2-μm CCD/CMOS fabrication. The device incorporates a matrix of charge injection device elements which hold a matrix of charge encoding the synapse strengths. A vector-matrix multiplier with simple charge-domain multiply-accumulate units has been implemented. The device computes the product of a binary vector and an analog matrix of charge, providing an analog output vector. At a clock rate of 1 MHz, the fabricated device computes 64 million binary/analog multiply accumulates per second in a very small area. The matrix refresh time is small compared to the refresh period

Keywords

CMOS integrated circuits; analogue computer circuits; charge-coupled device circuits; multiplying circuits; neural nets; 1 MHz; CCD/CMOS fabrication; analog matrix; analog output vector; binary vector; charge injection device elements; charge-domain multiply-accumulate units; matrix refresh time; mixed analog/digital neural network chip; parallel analog CCD/CMOS neural network IC; synapse strengths; vector-matrix multiplier; Analog computers; Analog integrated circuits; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS integrated circuits; Charge coupled devices; Clocks; Encoding; Fabrication; Neural networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on

Conference_Location

Seattle, WA

Print_ISBN

0-7803-0164-1

Type

conf

DOI

10.1109/IJCNN.1991.155219

Filename

155219