DocumentCode :
2767544
Title :
A High Performance, Parallel Architecture For The Least Squares Method
Author :
Ko, Hak-Lim ; Alexander, Winser E.
Author_Institution :
Hoseo University, Chung Narn, Korea 336-795
fYear :
1996
fDate :
15-15 May 1996
Firstpage :
57
Lastpage :
60
Keywords :
Array signal processing; Computational modeling; Computer architecture; Digital signal processing chips; Least squares methods; Mathematics; Matrices; Navigation; Parallel architectures; Systolic arrays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA, USA
Print_ISBN :
0-7803-3073-0
Type :
conf
DOI :
10.1109/ISCAS.1996.598476
Filename :
598476
Link To Document :
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