FPGA-Based Efficient Design Approach for Large-Size Two´s Complement Squarers

This paper presents an optimized design approach of two´s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on Baugh-Wooley´s algorithm, which partitions the multiplication into unsigned and signed sections. To achieve efficient implementation, a set of optimized schemes for the realization of multi-level additions of the partial products is proposed. Our approach has been evaluated through the implementation of squarers for operands with sizes ranging from 20 to 128 bits. The designs are synthesized and implemented on Xilinx´ Spartan-3 with ISE 8.1 design platform and compared with the standard implementation, and with Xilinx´ IP Core. The results indicate that our approach offers substantial LUT savings by up to 52% with an average delay reduction of 13%. The usage of the number of embedded multipliers is reduced by 38% compared with the standard schemes.