A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing

This paper presents a computationally-efficient design and implementation technique for fading channel simulators. Our fixed-point implementation of a Rayleigh fading channel simulator on a field-programmable gate array (FPGA) utilizes only 4% of the configurable slices, 19% of the dedicated multipliers, and 2% of the on-chip memory blocks, while generating 12.5 million statistically accurate fading variates per second. The designed channel emulator can be parameterized to simulate a wide variety of different channel characteristics over bandwidths of up to 12.5 MHz. The compact simulator can also be instantiated multiple times to assess the performance of communication systems over multiple-input multiple-output (MIMO) channels.