Interface traps and oxide traps under NBTI and PBTI in advanced CMOS technology with a 2nm gate-oxide

This work gives an insight of the degradation mechanisms during negative and positive bias temperature instability in advanced CMOS technology with a 2nm gate-oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. NBTI and PBTI in NMOS and PMOS have been compared a possible explanation for all configurations has been suggested. Relaxation and temperature effects under NBTI were also investigated showing different behaviors of the two components of threshold voltage shift, i.e. the interface traps and the oxide traps.