Breakdown walk-in: a new PMOS failure mode in high power BiCMOS applications

Today\´s power management devices frequently require operation in the 50V to 100V range based on F. de Pestel et al., (2003). These circuits implements a BiCMOS process that combine low to medium voltage (5-15V) with high voltage devices. In these applications the high voltage PMOS must be able to operate at high currents, voltage (e.g. 80V) and temperatures (150°C) while sustaining a drain breakdown voltage well in excess of the device operating voltage. Because of the high voltages, currents and temperatures seen by these devices the long term reliability is a key concern. This paper focuses on an HV-PMOs device failure mode identified during high temperature operational life testing that resulted in functional quiescent current failure. This paper differs from previous work in that it presents data on a new PMOS failure mechanism "breakdown voltage walk-in" not yet discussed in the literature.