DocumentCode :
2768437
Title :
A parallel architecture for high speed data compression
Author :
Storer, James A. ; Reif, John H.
Author_Institution :
Dept. of Comput. Sci., Brandeis Univ., Waltham, MA, USA
fYear :
1990
fDate :
8-10 Oct 1990
Firstpage :
238
Lastpage :
243
Abstract :
The authors discuss textural substitution methods. They present a massively parallel architecture for textural substitution that is based on a systolic pipe of 3839 identical processing elements that forms what is essentially an associative memory for strings that can learn new strings on the basis of the text processed thus far. The key to the design of this architecture is the formulation of an inherently top-down serial learning strategy as a bottom-up parallel strategy. A custom VLSI chip for this architecture that is capable of operating at 320-Mb/s has passed all simulations and is being fabricated with 1.2-μm double-metal technology
Keywords :
VLSI; application specific integrated circuits; data compression; microprocessor chips; parallel architectures; 1.2 micron; 320 Mbit/s; associative memory; bottom-up parallel; custom VLSI chip; data compression; double-metal technology; identical processing elements; massively parallel architecture; strings; systolic pipe; textural substitution; top-down serial learning; Associative memory; Compression algorithms; Computer science; Costs; Data communication; Data compression; Decoding; Parallel architectures; Prototypes; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Frontiers of Massively Parallel Computation, 1990. Proceedings., 3rd Symposium on the
Conference_Location :
College Park, MD
Print_ISBN :
0-8186-2053-6
Type :
conf
DOI :
10.1109/FMPC.1990.89465
Filename :
89465
Link To Document :
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