DocumentCode :
2768891
Title :
Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit
Author :
Calderón, Humberto ; Vassiliadis, Stamatis
Author_Institution :
Electrical Engineering Dept.,EEMCS,TU Delft, The Netherlands
fYear :
2006
fDate :
Sept. 2006
Firstpage :
311
Lastpage :
316
Abstract :
In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The prototyped hardware unit accommodates 4 dense or sparse matrix inputs and performs computations in a space parallel design achieving 4 multiplications and up to 12 additions at 120 MHz over an xc2vp100-6 FPGA device, reaching a throughput of 1.9 GOPS. A total of 11 units can be integrated in the same FPGA chip, achieving a performance of 21 GOPS.
Keywords :
Concurrent computing; Design engineering; Field programmable gate arrays; Hardware; Home computing; Laboratories; Prototypes; Sparse matrices; Throughput; World Wide Web;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application-specific Systems, Architectures and Processors, 2006. ASAP '06. International Conference on
Conference_Location :
Steamboat Springs, CO
ISSN :
2160-0511
Print_ISBN :
0-7695-2682-9
Type :
conf
DOI :
10.1109/ASAP.2006.58
Filename :
4019534
Link To Document :
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