A power-area analysis of NoCs in FPGAs

In this paper, we present accurate analytic models for the area, delay and power of NoC routers realized in FPGA technology. Using these router models, we present accurate analytic models for the area, delay and power of two classes of NoC topologies, the Torus and Generalized-Hypercube, realized with the Altera Family of FPGAs. Several router designs are explored, including unpipelined and pipelined designs with arbitrary amounts of buffering. The accuracy of the analytic models are evaluated by excessive experimental results. Architectural choices such as NoC topology, buffer sizing, crossbar switch, degree of contraction and pipelining can be explored analytically.