DocumentCode :
2769587
Title :
A power-area analysis of NoCs in FPGAs
Author :
Marvasti, M. Binesh ; Szymanski, T.H.
Author_Institution :
Dept. of ECE, McMaster Univ., Hamilton, ON, Canada
fYear :
2012
fDate :
12-14 Sept. 2012
Firstpage :
295
Lastpage :
300
Abstract :
In this paper, we present accurate analytic models for the area, delay and power of NoC routers realized in FPGA technology. Using these router models, we present accurate analytic models for the area, delay and power of two classes of NoC topologies, the Torus and Generalized-Hypercube, realized with the Altera Family of FPGAs. Several router designs are explored, including unpipelined and pipelined designs with arbitrary amounts of buffering. The accuracy of the analytic models are evaluated by excessive experimental results. Architectural choices such as NoC topology, buffer sizing, crossbar switch, degree of contraction and pipelining can be explored analytically.
Keywords :
field programmable gate arrays; network routing; network topology; network-on-chip; Altera family; FPGA technology; NoC routers; NoC topology; buffer sizing; crossbar switch; generalized-hypercube; power-area analysis; router models; torus-hypercube; unpipelined designs; Analytical models; Delay; Field programmable gate arrays; Latches; Switches; Topology; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOC Conference (SOCC), 2012 IEEE International
Conference_Location :
Niagara Falls, NY
ISSN :
2164-1676
Print_ISBN :
978-1-4673-1294-3
Type :
conf
DOI :
10.1109/SOCC.2012.6398325
Filename :
6398325
Link To Document :
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