Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC

Today´s electronic devices are expected to be fully function, low power consumption and high performance. There are more and more functional modules integrated in a SoC chip. A three-dimension integrated circuit (3-D IC) is developed and in which two or more layers of active electronic components are integrated both vertically into a single circuit. In two-dimension IC, the memory size usually dominated and occupied the most of area. Besides, 3-D IC designs will deal with serious challenges in design space exploration and system validation. In this work, we analyze different system architectures, mainly the architecture of the stacking memory. To demonstrate our 3-D IC design techniques, the stacking memory approach is employed in our “3D-PAC (Parallel Architecture Core)” design. In 3D-PAC, we stack 512KB SRAM directly on top of the logic die which is heterogeneous multi-core computing platform for multimedia application purpose. Finally, we use ESL technology to demonstrate the performance improvement. The result shows that there is 34.89% of speed-up by using the stacking memory architecture.