A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs

Author

Shakir, Tahseen ; Sachdev, Manoj

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada

fYear

2012

fDate

12-14 Sept. 2012

Firstpage

66

Lastpage

71

Abstract

SoCs yield in nanometer CMOS technologies is largely governed by SRAM reliability. Sense amplifier (SA) is a crucial component in an SRAM macro. Mismatch variation in conventional SAs can cause SRAM read failure. The problem becomes worst when the SRAM array operates at low voltage. In this work we propose a timing-insensitive SA scheme featuring read-assist and write-back mechanisms. Carried out Monte Carlo simulations on a 500 mV typical 6T-SRAM column confirm the robustness of the proposed SA against up to 5σ mismatch variations. Owing to its read-assist feature, the proposed scheme offers 38% improvement in bitline differential voltage and 40% reduction in cell data level degradation.

Keywords

CMOS integrated circuits; Monte Carlo methods; SRAM chips; amplifiers; low-power electronics; system-on-chip; Monte Carlo simulations; SRAM array; SRAM macro; SRAM read failure; SRAM reliability; SoC yield; bitline differential voltage; cell data level degradation; low voltage-operated SRAM; mismatch variation; nanometer CMOS technology; read-assist write-back voltage sense amplifier; timing-insensitive SA scheme; typical 6T-SRAM column; voltage 500 mV; Computer architecture; Microprocessors; Resource description framework; Sensors; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference (SOCC), 2012 IEEE International

Conference_Location

Niagara Falls, NY

ISSN

2164-1676

Print_ISBN

978-1-4673-1294-3

Type

conf

DOI

10.1109/SOCC.2012.6398382

Filename

6398382