Title :
Run-time management of custom instructions on a partially reconfigurable architecture
Author :
Lam, Siew-Kei ; Fan, Huang ; Srikanthan, Thambipillai ; Jigang, Wu
Author_Institution :
Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
Abstract :
Run-time reconfiguration can increase the cost efficiency and hardware specialization of reconfigurable processors by dynamically changing the configuration of the reconfigurable logic to the required functionality. In this paper, we propose a scheme for managing the runtime reconfiguration of custom instructions on a partially reconfigurable architecture that incorporates multi-bit logic blocks. The proposed scheme relies on the dynamic execution profile to replace the functionality of the logic blocks with the goal of minimizing the overall reconfiguration overhead. Experimental results show that the proposed scheme for runtime customization can lead to an average speedup of 3 times and average area savings of over 30% when compared to a method that relies on compile-time customization.
Keywords :
field programmable gate arrays; microprocessor chips; reconfigurable architectures; FPGA; compile-time customization; custom instruction; field programmable gate arrays; multibit logic blocks; partially reconfigurable processor architecture; reconfigurable logic; run-time reconfiguration management; Conference management; Costs; Field programmable gate arrays; Hardware; Microprocessors; Multiplexing; Multiprocessor interconnection networks; Reconfigurable architectures; Reconfigurable logic; Runtime;
Conference_Titel :
Electronic Design, 2008. ICED 2008. International Conference on
Conference_Location :
Penang
Print_ISBN :
978-1-4244-2315-6
Electronic_ISBN :
978-1-4244-2315-6
DOI :
10.1109/ICED.2008.4786687