Title :
A clock recovery and data regeneration sub-system for gigabit optical systems
Author :
McCullagh, Michael J.
Author_Institution :
BT Labs., Ipswich, UK
Abstract :
A number of clock recovery and data regeneration sub-systems have been designed and implemented to accompany a suite of `Light to logic´ optical receivers for operation at 0.622, 1.1, 1.5 and 2.4 Gbit/s data rates. These sub-systems employ three fully custom designed GaAs ICs, two of which are used in a high speed phase locked loop. The 1.1 Gbit/s sub-system has been used as part of a multi-media system demonstrator and its design, implementation and characterisation are reported in this paper
Keywords :
application specific integrated circuits; clocks; optical communication equipment; phase-locked loops; 0.622 to 2.4 Gbit/s; Light to Logic optical receivers; PLL; clock recovery; data regeneration sub-system; fully custom designed; gigabit optical systems; multi-media system demonstrator;
Conference_Titel :
Gigabit Logic Circuits, IEE Colloquium on
Conference_Location :
London
