Porous silicon device modeling and linearisation technique

This paper presents an approach for porous silicon device modeling by using porous silicon as a distributive RC network which will enable the simulation of a porous silicon sensor using VLSI CAD tools. Porous silicon based sensors are compatible to silicon IC processing and can be integrated on the same chip along with its signal processing unit. To make a smart sensor, along with device modeling, a linearisation scheme has also been presented, assuming a non linear response of the sensor. The scheme provides a digital path for the non-linearity correction of the sensor response but in an analog domain. The entire scheme has been simulated using T-SPICE.