Practical considerations for designing ASICs which incorporate scan path and JTAG techniques

In order for designs to be successfully tested on a production tester certain design rules must be obeyed. The rules fall into two categories based upon whether edge sensitive scan is being used or level sensitive scan is being used. Design for test considerations discussed include: verification of scan vectors; determination of the number of test vectors generated; testing of RAM and ROM blocks; functional testing; time to generate vectors; and boundary scan