An improved power MOSFET macro model for SPICE simulation

The SPICE MOSFET model was originally designed for modeling small signal lateral MOSFETs. Due to structural differences between small signal IC FETs and large geometry vertical FETs, the model is not able to simulate a power MOSFET accurately. Several macro models have been developed to overcome this problem. These models have served power designers well. However, inaccuracies in the gate charge and switching time characteristics cannot satisfy the needs of designers in the simulation of modern high frequency power supply design. To improve the accuracy of gate charge and switching time characteristics, a new model is developed based on the approach proposed by C.E. Cordonnier. In the new model an arbitrary current source is used to model the nonlinear gate to drain capacitance, Cgd. To improve simulation efficiency, the model avoids the use of any switches, which often cause voltage discontinuities. The model is fully tested in a variety of test circuits and results are compared to data sheet information to demonstrate the accuracy of this new model