Operating-margin-improved SRAM with column-at-a-time body-bias control technique

This paper describes a column-at-a-time body bias control technique to improve SRAM operating margins. This technique controls the body bias of the load MOS in SRAM memory cells according to SRAM operation. A 90-nm prototype chip using this technique demonstrates an improved operating margin, and the SRAM with this technique can endure 0.7-sigma more V_th variation.