Title :
A multistandard Σ-Δ fractional-N frequency synthesizer for 802.11a/b/g WLAN
Author :
Bonfanti, A. ; Samori, C. ; Lacaita, A.L.
Author_Institution :
Politecnico di Milano, Milano
Abstract :
A multistandard WLAN fractional-N frequency synthesizer is implemented in 0.13-mum CMOS. The PLL is able to generate carrier frequency for 802.11a/b/g and Hiper- LAN2 standards. Given the wide tuning range required, the VCO adopts a switched tuning LC tank together with an Adaptive Frequency Calibration (AFC) technique. Measured integral phase noise is less than 3deg rms and the 40-MHz reference spurs are below -40 dBc. Lock time is less than 200 musec. The power consumption is about 50 mW from a 1.2- V supply.
Keywords :
CMOS integrated circuits; IEEE standards; frequency synthesizers; phase locked loops; voltage-controlled oscillators; wireless LAN; 802.11abg WLAN; CMOS; adaptive frequency calibration; delta-sigma fractional-N frequency synthesizer; multistandard WLAN fractional-N frequency synthesizer; phase locked loop; power 50 mW; size 0.13 micron; voltage 1.2 V; voltage-controlled oscillator; Automatic frequency control; Calibration; Frequency synthesizers; Noise measurement; Phase locked loops; Phase measurement; Phase noise; Tuning; Voltage-controlled oscillators; Wireless LAN;
Conference_Titel :
Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European
Conference_Location :
Munich
Print_ISBN :
978-1-4244-1125-2
DOI :
10.1109/ESSCIRC.2007.4430346
