DocumentCode :
2772507
Title :
Yield optimization with energy-delay constraints in low-power digital circuits
Author :
Cao, Yu ; Qin, Huifang ; Wang, Ruth ; Friedberg, Paul ; Vladimirescu, Andrei ; Rabaey, Jan
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear :
2003
fDate :
16-18 Dec. 2003
Firstpage :
285
Lastpage :
288
Abstract :
As circuit parametric variations aggravate in advanced technology, yield emerges as an important figure-of-merit in circuit design. Based on a 130 nm technology, the yield-energy-delay tradeoffs in low-power circuit optimization are investigated. Using a log-normal statistical model, Monte-Carlo analyses are performed on typical circuit examples, including an inverter chain, NAND gate, and 4-bit adder. While energy reduction can be effectively achieved by tuning supply voltage (Vdd), threshold voltage (Vth), and device width (W), circuit yield degrades during this process. On the other hand, it is observed that performance variability is relatively insensitive to circuit topology and device length (L). Design guidelines for optimizing yield in the presence of parametric variations and energy-delay constraints are proposed.
Keywords :
Monte Carlo methods; circuit optimisation; digital circuits; network topology; 130 nm; 4-bit adder; Monte-Carlo analysis; NAND gate; circuit design; circuit parametric variations; circuit topology; device width; energy-delay constraints; low-power digital circuits; power circuit optimization; threshold voltage; tuning supply voltage; yield optimization; Adders; Circuit optimization; Circuit synthesis; Circuit topology; Constraint optimization; Degradation; Digital circuits; Inverters; Performance analysis; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN :
0-7803-7749-4
Type :
conf
DOI :
10.1109/EDSSC.2003.1283533
Filename :
1283533
Link To Document :
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