DocumentCode
2772913
Title
Analysis of low-dropout regulator topologies for low-voltage regulation
Author
Lau, Sai Kit ; Leung, Ka Nang ; Mok, Philip K T
Author_Institution
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China
fYear
2003
fDate
16-18 Dec. 2003
Firstpage
379
Lastpage
382
Abstract
The design considerations of integrated CMOS low-voltage low-dropout regulators are addressed in this paper. The limitations of a generic LDO based on dominant-pole compensation are discussed. Then, LDO with a voltage-buffer stage and the corresponding problems in low-voltage design are discussed. Finally, an advanced compensation technique based on nested Miller compensation for achieving high performances is presented.
Keywords
CMOS integrated circuits; voltage regulators; dominant pole compensation; integrated CMOS low voltage low dropout regulators; nested Miller compensation; voltage-buffer stage; Batteries; CMOS technology; Circuit noise; Paramagnetic resonance; Personal digital assistants; Poles and zeros; Power supplies; Regulators; Topology; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN
0-7803-7749-4
Type
conf
DOI
10.1109/EDSSC.2003.1283554
Filename
1283554
Link To Document