Embedded Electronics Systems for Training Support Vector Machines

Training support vector machines (SVMs) requires efficient architectures, endowed with agile memory handling and specific computational features. Such a process is often supported by embedded implementations on dedicated machinery, for example in applications requiring on-line training abilities. The paper presents a general approach to the efficient implementation of SVM training on digital signal processor (DSP) devices. The methodology optimizes efficiency by a twofold approach: first, it suitably adjusts an established, effective training algorithm for large data sets; secondly, it reformulates the algorithm to best exploit the computational features of DSP devices and boost efficiency accordingly. Experimental results tackle the training problem of SVMs by using a high-end DSP architecture on real-world benchmarks, and confirm both the effectiveness and the general validity of the approach.