DocumentCode
2774149
Title
High-level low power FPGA design methodology
Author
Wolff, Francis G. ; Knieser, Michael J. ; Weyer, Dan J. ; Papachristou, Chris A.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA
fYear
2000
fDate
2000
Firstpage
554
Lastpage
559
Abstract
High-level design for low power is difficult to accomplish especially for FPGA designs. Presents a design technique that uses pre-computed tables that characterize the RTL and Intellectual Property (IF) components to estimate power. Actual tables were computed and the low-power design technique demonstrated. The results show that a lower power design can be achieved given this design methodology
Keywords
FIR filters; digital filters; field programmable gate arrays; high level synthesis; industrial property; table lookup; FIR; FPGA design; Intellectual Property; RTL; digital filters; high level design; look up table; low power methods; pre-computed tables; Application specific integrated circuits; Costs; Design methodology; Digital filters; Electronics packaging; Energy consumption; Field programmable gate arrays; Finite impulse response filter; Intellectual property; Logic;
fLanguage
English
Publisher
ieee
Conference_Titel
National Aerospace and Electronics Conference, 2000. NAECON 2000. Proceedings of the IEEE 2000
Conference_Location
Dayton, OH
Print_ISBN
0-7803-6262-4
Type
conf
DOI
10.1109/NAECON.2000.894960
Filename
894960
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