Title :
Low power testing by test vector ordering with vector repetition
Author :
Bellos, M. ; Bakalis, D. ; Nikolos, D. ; Kavousianos, X.
Author_Institution :
Dept. of Comput. Eng. & Inf., Patras Univ., Greece
Abstract :
Test vector ordering with vector repetition has been presented as a method to reduce the average as well as the peak power dissipation of a circuit during testing. Based on this method, in this paper we present some techniques that can be used to further reduce the average power dissipation. Experimental results validate that the proposed techniques achieve considerable savings in energy and average power dissipation while reducing the length of the resulting test sequences compared to the original method.
Keywords :
automatic test pattern generation; combinational circuits; logic testing; low-power electronics; average power dissipation; combinational circuit; low power testing; parameter threshold; peak power dissipation; root selection; test sequences length; test vector ordering; vector repetition; zero-delay model; Circuit testing; Delay; Energy dissipation; Power dissipation; Power engineering and energy; Power system reliability; Scholarships; Switching circuits; System testing; TV;
Conference_Titel :
Quality Electronic Design, 2004. Proceedings. 5th International Symposium on
Print_ISBN :
0-7695-2093-6
DOI :
10.1109/ISQED.2004.1283674
