DocumentCode :
2776769
Title :
Testing linear and non-linear analog circuits using moment generating functions
Author :
Sindia, Suraj ; Agrawal, Vishwani D. ; Singh, Virendra
Author_Institution :
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
fYear :
2011
fDate :
27-30 March 2011
Firstpage :
1
Lastpage :
6
Abstract :
Circuit under test (CUT) is treated as a transformation on the probability density function of its input excitation, which is, a continuous random variable (RV) of gaussian probability distribution. Probability moments of the output, which is now the transformed RV, is used as a metric for testing catastrophic and parametric faults in circuit components that make up the CUT. Use of probability moments as circuit test metric with white noise excitation as input addresses three important problems faced in analog circuit test, namely: 1) Reduces complexity of input signal design, 2) Increases resolution of fault detection, and 3) Reduces production test cost as it has no area overhead and marginally reduces test time. We develop the theory, test procedure and report SPICE simulation results of the proposed scheme on a benchmark elliptic filter. With the proposed scheme, we are able to detect all catastrophic faults and single parametric faults that are off from their nominal value by just over 10%. Method reported in this paper paves way for future research in circuit diagnosis, leveraging moments of the output to diagnose parametric faults in analog circuits.
Keywords :
Gaussian distribution; analogue integrated circuits; elliptic filters; integrated circuit testing; Gaussian probability distribution; SPICE simulation; analog integrated circuits; benchmark elliptic filter; catastrophic testing; circuit components; circuit under test; continuous random variable; fault detection; linear analog circuit testing; moment generating functions; nominal value; nonlinear analog circuit testing; parametric faults testing; probability density function; probability moments; white noise excitation; Analog circuits; Circuit faults; Equations; Mathematical model; Testing; White noise;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Workshop (LATW), 2011 12th Latin American
Conference_Location :
Porto de Galinhas
Print_ISBN :
978-1-4577-1489-4
Type :
conf
DOI :
10.1109/LATW.2011.5985915
Filename :
5985915
Link To Document :
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