Title :
Packaging challenges in the design of a 800 Mbps source-synchronous simultaneous bi-directional parallel interface
Author :
Bandyopadhyay, Jaya ; Cases, Moises
Author_Institution :
IBM Corp., Austin, TX, USA
Abstract :
This paper describes the packaging issues, challenges and design solutions for a high-speed, point-to-point, low latency, high-bandwidth, simultaneous bi-directional interface used for board-to-board and box-to-box coupling of the system bus and/or I/O bus. Major design issues such as attenuation, crosstalk, delay skew, impedance control and inter-symbol interference for long and parallel external interconnection are discussed, along with the timing and jitter budget allocation. Design guidelines are provided for a 3.2 MB/sec physical interface using two bytes of simultaneous bi-directional data operating at 400 MHz double data transfer rates (DDR)
Keywords :
crosstalk; delays; electric impedance; integrated circuit interconnections; integrated circuit packaging; intersymbol interference; jitter; multiprocessor interconnection networks; parallel architectures; system buses; timing; 3.2 Mbit/s; 400 MHz; 800 Mbit/s; I/O bus; attenuation; bandwidth; board-to-board coupling; box-to-box coupling; crosstalk; delay skew; design; design guidelines; double data transfer rates; impedance control; inter-symbol interference; jitter budget allocation; latency; packaging; parallel external interconnection; physical interface; point-to-point simultaneous bi-directional interface; simultaneous bi-directional data; source-synchronous simultaneous bi-directional parallel interface; system bus; timing budget allocation; Attenuation; Bidirectional control; Crosstalk; Delay; Guidelines; Impedance; Interference; Packaging; System buses; Timing jitter;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2000, IEEE Conference on.
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-7803-6450-3
DOI :
10.1109/EPEP.2000.895481
