Performance improvement using on-board wires for on-chip interconnects

Author

Naeemi, Azad ; Zarkesh-Ha, Payman ; Patel, Chirag S. ; Meindl, James D.

Author_Institution

Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2000

fDate

2000

Firstpage

325

Lastpage

328

Abstract

Utilizing a stochastic global-net length distribution for a projected giga-scale integration (GSI) chip in year 2011, the number of total off-chip layers and pads required for a specified decrease of the maximum on-chip interconnect length are calculated. For example, by adding four off-chip layers to the on-chip interconnects of the projected microprocessor, the global clock frequency can be increased from 3 GHz to 4 GHz, which is the maximum possible value limited by the time of flight delay

Keywords

ULSI; clocks; delays; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit packaging; microprocessor chips; stochastic processes; 3 GHz; 4 GHz; GSI chip; giga-scale integration chip; global clock frequency; maximum on-chip interconnect length; microprocessor; off-chip layers; on-board wires; on-chip interconnects; performance improvement; stochastic global-net length distribution; time of flight delay; total off-chip layers/pads; Clocks; Delay effects; Frequency; Microprocessors; Packaging; Repeaters; Stochastic processes; Wafer scale integration; Wires; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2000, IEEE Conference on.

Conference_Location

Scottsdale, AZ

Print_ISBN

0-7803-6450-3

Type

conf

DOI

10.1109/EPEP.2000.895555

Filename

895555