Title :
Automatic Testbench Generation for Rearchitected Designs
Author_Institution :
Intrinsity Inc., Austin, TX
Abstract :
This paper describes a tool for automated testbench generation used to compare a design against a cycle-accurate RTL reference model. The advantage of this tool is that it allows testing of design modules as they become ready, using chip-level test suites or random tests. The tool is able to handle arbitrary encodings of RTL signals to design signals, retiming, and even changes to the module boundaries.
Keywords :
automatic testing; logic circuits; logic design; logic testing; automatic testbench generation; chip-level test suites; cycle-accurate RTL reference model; rearchitected designs; Automatic testing; CMOS logic circuits; Clocks; Encoding; Leg; MOS devices; MOSFETs; Microprocessors; Signal design; Switches; rearchitected designs; retiming; testbench; testbench generation;
Conference_Titel :
Microprocessor Test and Verification, 2007. MTV '07. Eighth International Workshop on
Conference_Location :
Austin, TX
Print_ISBN :
978-0-7695-3241-7
DOI :
10.1109/MTV.2007.11
