High performance classifier architectures for binary image processing

Adaptability and high performance are prerequisites for cost-effective automatic industrial inspection and other product handling systems. The specification of appropriate systems therefore demands the development both of high performance algorithms and efficient techniques for implementation, together with a means of matching algorithms and implementational infrastructure. Transputer arrays offer a potentially very effective infrastructure for the implementation of pattern classification algorithms, which often embody inherent parallelism in their structure. The paper investigates ways in which a number of classification algorithms, particularly those directly optimised for the processing of binary images and applicable to automatic inspection tasks, can be mapped to an array of transputers to provide a real-time environment for classification processing. It is shown how the parallel implementation of a multilevel hierarchical architecture can offer significant benefits in defining the relationship between computational complexity (and therefore attainable processing speeds) and error rate performance