Title :
Macro-Model for Post-Breakdown 90NM and 130NM Transistors and its Applications in Predicting Chip-Level Function Failure after ESD-CDM Events
Author :
Chen, Tze Wee ; Ito, Choshu ; Loh, William ; Wang, Wei ; Mitra, Subhasish ; Dutton, Robert W.
Author_Institution :
Centre for Integrated Syst., Stanford Univ., CA
Abstract :
A post-breakdown transistor macro-model for 90nm and 130nm technologies is presented and experimentally verified. Oxide breakdown does not necessarily imply function failure. The location of breakdown within the circuit is also important. A simulation methodology implementing this macro-model is presented. This tool can be used to predict function failure for three different system-on-chip (SoC) design examples. Simulations agree well with failure analysis (FA) observations, verifying the validity of the macro-model
Keywords :
failure analysis; integrated circuit design; semiconductor device breakdown; semiconductor device models; semiconductor device reliability; system-on-chip; transistors; 130 nm; 90 nm; ESD-CDM events; chip-level function failure; failure analysis; inductive coupling; oxide breakdown; post-breakdown transistors macromodel; system-on-chip design; Breakdown voltage; Circuit simulation; Coupling circuits; Degradation; Electric breakdown; Geometry; Integrated circuit modeling; Large scale integration; Solid modeling; Stress; ESD-CDM; chip-level function failure prediction; inductive coupling; post-breakdown transistor macro-model;
Conference_Titel :
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international
Conference_Location :
Phoenix, AZ
Print_ISBN :
1-4244-0919-5
Electronic_ISBN :
1-4244-0919-5
DOI :
10.1109/RELPHY.2007.369872
