DocumentCode
278289
Title
ELSA-a wafer scale image processing system
Author
Shi, Ling ; Ivey, Peter A. ; Harbridge, John R.
Author_Institution
Dept. of Electron. & Electr. Eng., Sheffield Univ., UK
fYear
1991
fDate
33350
Firstpage
42491
Lastpage
42497
Abstract
Describes the architecture of the ELSA Processor, a massively parallel SIMD/MSIMD machine implemented in wafer scale technology, and its capability to implement many algorithms in image processing, pattern recognition, signal processing, etc. The ELSA Processor contains 2304 bit serial processing elements (PEs) configured in a two dimensional array. The wafer employs a 1.2 μm double metal CMOS process and will operate at a clock speed of up to 20 MHz. For eight bit data, additions can be carried out at about 5 billion per second
Keywords
computerised pattern recognition; computerised picture processing; computerised signal processing; parallel architectures; ELSA Processor; SIMD/MSIMD; image processing; pattern recognition; signal processing; wafer scale technology;
fLanguage
English
Publisher
iet
Conference_Titel
Parallel Architectures for Image Processing Applications, IEE Colloquium on
Conference_Location
London
Type
conf
Filename
181499
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