Title :
Impact of Bottom Interfacial Layer on the Threshold Voltage and Device Reliability of Fluorine Incorporated PMOSFETS with High-K/Metal Gate
Author :
Choi, Kisik ; Lee, Taeho ; Barnett, Joel ; Harris, Harlan R. ; Kweon, Seungsoo ; Young, Chadwin ; Bersuker, Gennadi ; Choi, Rino ; Song, Seung Chul ; Lee, Byoung Hun ; Jammy, R.
Author_Institution :
SEMATECH, Austin, TX
Abstract :
The effect of F implantation combined with high quality bottom interfacial layer has been investigated in terms of threshold voltage reduction and improvement of device performance of TaCN/AlN/HfSiOx gate stacks for PMOS application. Threshold voltage becomes more positive as AlN, F implantation, and thermally grown interfacial layer steps are added. It is found that F accumulates near the interface with the Si substrate and the observed Vth shift has been attributed to the passivation of positively charged defects in the dielectric stack and additional negative charge associated with F atoms. Thermally grown interfacial layer combined with F implantation resulted in excellent device parameters and reliability as well as lower PMOS Vth due to inherently lower defect density and defect passivation effect by F atoms.
Keywords :
MOSFET; aluminium compounds; hafnium compounds; interface states; passivation; semiconductor device reliability; silicon; tantalum compounds; TaCN-AlN-HfSiO; bottom interfacial layer; defect density; defect passivation; device reliability; dielectric stack; pMOSFETs; Annealing; Atomic layer deposition; Dielectric substrates; Electrodes; High K dielectric materials; High-K gate dielectrics; Jamming; MOSFETs; Passivation; Threshold voltage;
Conference_Titel :
Reliability physics symposium, 2007. proceedings. 45th annual. ieee international
Conference_Location :
Phoenix, AZ
Print_ISBN :
1-4244-0919-5
Electronic_ISBN :
1-4244-0919-5
DOI :
10.1109/RELPHY.2007.369918