DocumentCode
278339
Title
An integrated methodology for the design and test of circuits using ScanPlus
Author
Boswell, Andy
fYear
1991
fDate
33374
Firstpage
42401
Lastpage
42408
Abstract
This paper describes a structured test methodology which meets the test challenge of large digital ASICs. The CAD system ScanPlus is described which supports this methodology in a seamless test flow from netlist to test tape
fLanguage
English
Publisher
iet
Conference_Titel
Design for Testability, IEE Colloquium on
Conference_Location
London
Type
conf
Filename
181573
Link To Document