The design of a C-testable parallel multiplier using a graph-theoretic approach

Describes a novel graph-theoretic test pattern generation technique for a parallel multiplier. The graph can be modified by making use of the `don´t care´ cell input vectors without affecting the overall array function such that the array structure becomes C-testable. The required number of test patterns and test modes to test this array is 14 with 14 input vectors and 5 respectively compared with 16 test patterns and 16 input vectors and 6 test modes in the current literature. Using the concept of C-testability the authors can minimize the extra hardware for testing iterative array structures