An abstract approach to VLSI test

Inherent imperfections in the VLSI fabrication processes mean that even logically correct designs may be fabricated as faulty chips. Testing of devices is therefore essential. The author considers the use of CCS to deduce testability features of VLSI. He shows first that a natural correspondence exists between circuit designs and a certain class of processes in CCS (a popular abstract language for reasoning about concurrent systems), and then use this correspondence to show how standard faults can economically be represented, and reasoned about. Questions considered include: given such and such a fault, when can it be detected? If a fault is detectable, to what extent can its location be identified? And given a design, can one construct a logically equivalent process of improved testability?