A transient analysis of power distribution noise in highly synchronous CMOS integrated circuits

A novel simulation method has been developed to assess the magnitude and nature of power distribution noise in CMOS digital integrated circuits. The method has identified limits relating to the performance and/or size of a highly synchronous array-based architecture involving the simultaneous switching of 340000 devices. The simulation method has been developed for application to a non-array-based architecture. The analysis has identified performance limits which, for the memory reticle, are 60% lower than the required design specification and, for the processor reticle, are 40% in excess of the required design specification. For each architecture, the method has predicted the extent to which non-standard technology variants can be expected to improve performance