Multi-Junction Fault Tolerance Architecture for Nanoscale Crossbar Memories

Nanoscale elements are fabricated using bottom-up processes, and as such are prone to high levels of defects. Therefore, fault-tolerance is crucial for the realization of practical nanoscale devices. In this paper, we investigate a fault tolerance scheme that utilizes redundancies in the rows and columns of a nanoscale crossbar molecular switch memory array. In particular, we explore the performance tradeoffs of time delay, power, and reliability for different amounts of redundancies. The results indicate an increase in fault-tolerance with small increases in delay and area utility.